1. Field of the Invention
The invention generally relates to a composition and method for planarizing materials on a substrate surface.
2. Background of the Related Art
In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited on or removed from a surface of a substrate. Thin layers of conducting, semiconducting, and dielectric materials may be deposited by a number of deposition techniques. Common deposition techniques in modern processing include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and now electrochemical plating (ECP).
As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials. Planarization is also useful in forming features on a substrate by removing excess deposited material used to fill the features and to provide an even surface for subsequent levels of metallization and processing.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. CMP utilizes a chemical composition, typically a composition or other fluid medium, for selective removal of material from substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing pad. The pad is moved relative to the substrate by an external driving force. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of the substrate and the polishing pad while dispersing a polishing composition, or slurry, to effect both chemical activity and mechanical activity and consequential removal of material from the surface of the substrate.
Conventional CMP processes are performed using an abrasive article, such as a polishing composition, or slurry, containing abrasive particles in a reactive solution with a conventional polishing pad. Alternatively, the abrasive article can be a fixed abrasive article, such as a fixed abrasive polishing pad, which may be used with a CMP composition that does not contain abrasive particles. A fixed abrasive article typically comprises a backing sheet with a plurality of geometric abrasive composite elements adhered thereto.
Copper is becoming a metal of choice to form electronic devices on semiconductor substrates. However, copper is difficult to pattern and etch and new processes and techniques, such as damascene or dual damascene processes, are being used to form copper substrate features. In damascene processes, a feature is defined in a dielectric material and subsequently filled with copper. A barrier layer is deposited conformally on the surfaces of the features formed in the dielectric layer prior to deposition of copper material. Copper material is then deposited over the barrier layer and the surrounding field. The copper material deposited on the field is removed by CMP processes to form a copper filled feature in the dielectric material.
Conventionally, in polishing substrates having copper features, the copper material is polished to expose the barrier layer between the copper features, and then the barrier layer is polished to expose the underlying dielectric layer between the copper features. One challenge that is presented in polishing copper materials is that the interface between the conductive material and the barrier layer is generally non-planar. Further, the conductive material and the barrier materials are often removed from the substrate surface at different rates, both of which can result in excess conductive material being retained as residues on the substrate surface. Additionally, the substrate surface may have different surface topography, depending on the density or size of features formed therein, which removes copper material at different removal rates along the substrate surface and makes effective conformal removal of copper material from the substrate surface difficult to achieve.
One solution to removing all of the desired copper material from the substrate surface is overpolishing the substrate surface. However, overpolishing of some materials can result in the formation of topographical defects, such as concavities or depressions in features, referred to as dishing, or excessive removal of dielectric material, referred to as erosion. The topographical defects from dishing and erosion can further lead to non-uniform removal of additional materials, such as barrier layer materials disposed thereunder, and produce a substrate surface having a less than desirable polishing quality. Additionally, chemical compositions used in copper CMP typically include multiple components such as oxidizing agents and complexing agents. The compositions may further include abrasive particles, such as colloidal silica, as the abrasive component. The components are typically combined prior to the delivery of the composition to the pad for polishing. The various components may interact with one another or otherwise degrade resulting in a less effective formulation. A typical pot life, e.g., the effective period of the composition, may be twenty-four (24) hours or less under certain polishing performance requirements.
Therefore, there exists a need for a method that improves planarizing a metal layer, such as a copper layer, on a substrate surface with a polishing composition. There is also a need for polishing compositions having an extended pot life.